Oscillator drift compensation



OCL 31, 1957 w. G. WALKER OSCILLATOR DRIFT COMPENSATION 3 Sheets-Sheet l Filed May 19, 1966 INVENTOR. WNsroN G. 6L/(ER aux@ ,a ,Orr-afNews.

I5 Sheets-Sheet 2 Filed May 19, 1966 @40.3

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INVENTOR l//vso/v G. Wulff@ www #W United States Patent ABSTRACT F THE DISCLOSURE The disclosed invention concerns highly accurate control of oscillator drift, during use of a standard frequency generator and after removal of the standard.

This invention relates generally to oscillator drift compensation, and more particularly concerns highly accurate control of oscillator drift during use of a standard frequency generator, and after removal of the standard.

It is a major object of the invention to provide an oscillator or clock that is drift compensated in such a way as to remain highly accurate over extended periods of time. For example, the invention makes possible drift rates as low as one part in one billion parts, per day, in the absence of connection to4 a frequency standard, through the provision of unusual methods of drift cornpensation as well as unusualdrift compensation apparatus. Such oscillators are needed for example in the fields of military and space communications and telemetry.

The basic method of the invention includes the vsteps of operating a generator to produce a signal frequency f1 to derive a compensated output version of j., of f1, comparing fo with the output fi of a frequency standard to derive a first Yerror signal related to the drift, using the er-ror signal in the operation upon f1 in such manner as to alterV fo for, reducing the error signal, generating a maintainable correction signal corresponding toa time derivative of the error signal, and also using the correction signal in the operation upon f1. Accordingly, 'when the standard is removed and the error signal no longer is derived, the correction signal is maintained to operate lupon f1 so as to correct for drift.

`In a preferred step of operating upon f1 to derive fo, multiple output signals of frequency f1 are produced as by a phase splitter, with the signals phase displaced so as to cancel if added; the multiple output signals are then variably amplitude modulated as a function of the above described error signal; and thereafter the amplitude modulated signals are combined to produce a phase modulated side band signal fo, i.e. the compensated output version fo 0f fi- Regarding the maintainable correction signal, it typically corresponds to substantially the first derivative with respect to time of the error signal, and it is used along with the principal error signal in the compensating operation upon f1. Further, for even higheraccuracy and better response, the invention contemplates that the maintainable correction signal may be made to correspond to substantially the second as Well as the lirst derivatives with respect to time of the principal error signal.

In its basic apparatus aspects, the invention contemplates the provision of a generator to produce a signal frequency f1 subject to drift, means operating upon f1 to derive a compensated version fo of f1, means to compare fo with the output f1 of a frequency standard to derive a first error signal relatedto the drift, and feedback channel means to transmit a Version of the error signal to the operating means in compensating relation so as to alter fo for reducing the error signal and to generate and transmit to the operating means a maintainable correction signal corresponding to a time derivative of the error signal. Typically, the operating means may preferably include phase shifting means responsive to the received signal frequency f1 to produce multiple outputs of frequency j, and respectively phase displaced so as to cancel if added, and means connected to be responsive to the error signal for selectively passing and variably amplitude modulating the multiple output signals and thereafter combining the amplitude modulated signals to produce the compensated output version fo. Y

The above referred to feedback channel means may include means to generate and transmit maintainable correction signals as described above in connection with the method aspects of the invention. Further, the first and second derivative generators may comprise variable pulse rate generators used in the unusually advantageous way or ways to be described in greater detail.

These'and other objects and advantages of the invention, as well as the details of illustrative embodiments, will be more fully understood from the following detailed description of the drawings in which:

FIG. 1 is a functional block diagram showing one form of oscillator drift compensation system incorporating the invention;

FIG. 2'illustrates circuit mechanization of that portion of FIG. 1 which operates upon f1 to derive fo;

FIG. 3 shows the manner in which compensated (fo) and standard (fi) pulses may be compared to derive a first error signal;

FIG. 4 illustrates a phase diagram showing division of the modulating or error signal into angular increments corresponding to variable control of the switches;

FIG. 5 is a tabulation correlating the FIG. 4 increments with switch closure; and

FIG. 6 is a diagram showing four output signals pro- Vduced from the carrier.

Referring first to FIG. l, a carrier signal source is indicated generally at 10, andv may for example include a crystal controlled oscillator or clock. The signal output from the source is indicated at 11, and may typically have generally sinusoidal Wave form:

A Sin (dlt the frequency of which may for example be in the megacycle range, and is defined as: Y

It is desired to accurately compensate for any slight frequency or phase drift of the output of 10, and for this purpose the signal 11 is passed to a phase modulator 12 which operates upon the input 11 to produce an output 13 version of f1 which may typically have the form:

An(f) Sin (Lari-wz)t (3) the frequency of which is defined as f2=$=fi+KaAR+AF As an example, f1 may be 106 cycles per second and it may drift at rates greater than l part in 109 per day. In this regard, a modulator control 14 operates to con- Itrol the modulator 12 in the manner to be later dean error signal input, AR and AF to be mitted by parallel channels `generally indicated at 21, but specifically illustrated as channels 16-1'9 in FIG. 2 for the case where the signals are phase displaced at 90 degree intervals. As tothe latter case, FIG. 6 shows four typical channel signals 16a, 17a, 18a and 19a in the case where they may have sinusoidal form, although numbers of channels other than four and signal wave forms other than sinusoidal are contemplated. Also, phase displacement of the signals may b e other than 90 degrees.

Further in accordance with the invention, the modulator 12 and control 14 may be considered to include means connected to be responsive to the error signal at 20 for selectively passing and variably amplitude modulating different of the output signals transmitted by channels 21 and thereafter combining the amplitude modulated signals to produce a suppressed carrier, phase modulated single side band signal for transmission at 13. That signal may be filtered at 22 to remove high frequency components introduced by the modulator switching, and limited at 23 to produce a single side band -phase modulated square wave at output f2 24. A one pole iilter is shown, although filters of other configurations are contemplated.

In the form of the invention illustrated in FIG. 2, the above means last referred to includes an attenuator network 25 having parallel resistors and parallel switches connected to selectively Vpass and variably attenuate different of the signals transmitted via channels 21. For example, as seen in FIG. 2, there are parallel primary switches 3.1-34, and resistors and switches deining first and second parallel banks and 36. Bank 35 includes three .parallel branches with a common input terminal 37, and bank 36 has three parallel branches with a common input terminal 38. A summing junction 39 4provides a common output terminal for the branches of both banks 35 and 36 in network 25. Each branch in the banks includes a resistor and a switch connected in series, the resistors being designated at 41-46, and the switches (called secondary switches) being indicated at 51-56.

The primary switches 31 and 32 are arranged to selectively connect and disconnect two of the phase shifter output signals, for example 16a and 18a, with the common input terminal 37 of bank 35, and primary switches 33 and 34 are arranged to selectively connect and disconnect two of the phase shifter output signals, for example 19a and 17a with the common input terminal 3 8 of bank 36. Switch control means 14a and 14b are responsive to the error signal aty 20 to operate the -primary switches 31,- 34 and secondary switches 51-56 respectively.

To better understand the operation of the FIG. 2 circuit, it will be understood that expression (3) above may be written as follows:

An(t) sin (w1 -|-w2)rn=An(t) [sin with cos n -t-cos urn sin n] (5) where, A(z) :amplitude of output at 13, which is a function of time, and is represented by the length of vector in FIG. 4

zangle between arbitrary equal time intervals tro,

z-l, et.

11=the angular displacement of modulating signal vector 60 at zn N13 In other words, looking at the right hand side of Equation 5, it is seen that the amount of the carrier cornponent 16a designated as A110) sin wlkt to be included in the output at time tn is represented by the expression cos n and the amount of the carrier component 19a designated as An(t) cos wlt to be included in the output at time tn is represented by the expression sin n.

Further, the desired phase modulation wz to correct for drift is seen to be derived by selective inclusion of the resistors 41-46 momentarily switched into signal passing and attenuating relation to the signals 16a-19a.

In FIG. 4, the modulating frequency f2 is assumed for purposes of illustration to be one cycle per second, represented by the vector 60 sweeping counterclockwise through 360 degrees in one second. Various secondary switches of attenuator network 25 are operated by the control 14 at 1/32 intervals, so that in the interval 0 to 1r/ 2 in FIG. 4 various of switches 51-56 of FIG. 2 will be operated at each of the vector angles represented by the times to, t1, t8. Various of secondary switches 51-56 will also be operated at 1/32 second intervals as the vector 60 sweeps through the remaining quadrants of the FIG. 4 circle. On the other hand, the open or closed states of the primary switches of network 25 are tabulated as follows:

Vector 60 position Primary Switches Primary Switches Open Close 0 to 90 32 and 34 31 and 33 to 180 31 and 34 32 and 33 to 270 3i and 33 32 and 34 270 to 360 32 and 33 31 and 34 Thus, switches 31-34 are variously operated each quarter second as vector 60 arrives at 90, 180, 270 and 360 positions. Also in FIGS. 2-5, the values of the resistors 41 to 46 are as follows, giving the proper weighting or attenuation in various combinations:

Unit of resistance In FIG. 5 are tabulated the open or closed states of the secondary switches 5 1-56 at vector angular positions to t8 in the rst quadrant. Switch positions for corcorresponding vector positions in the remaining quadants may be similarly determined. In general, the number of primary and secondary switches and resistors may be correlated to the selected time increment sampling of the phase split input signals.

Generally speaking, the value of the amplitude term A(t) in Equation 5 will fluctuate somewhat in value due to the discretely incremental or digital type functioning of the attenuator 25 as various of the switches are operated at each of the vector time positions to t8, etc. This fluctuation results in thev star pattern traced by the tip of vector 60 in FIG. 4. Limiter 23 removes these amplitude fluctuations, leaving the square wave axis crossings as the phase modulation on the signal f2. Low pass filter 22 is used to eliminate switching transients, i.e. it smooths the output.

The phase shifter network 15 is known in the art. Also, the switches 31-34 and 51-56 may be electronic, and may be suitably controlled at 14. Limiter 23 is standard, and the filter 22 may include a DC amplier with feedback capacitance and resistance as indicated in FIG. 3.

The signal f2 at 24 in FIG. 1 is next divided at 100 to produce the version fo of f2, the latter being a compensated version of f1 as will now be described. Referring briefly to FIG. 2, fo is compared as by comparator device 101 with the output fi of a frequency standard 140 to derive a first error signal AR related to the drift of f1; thereafter the error signal is used in the operation upon f1 (as by controlling the modulator 25) in such manner as to alter fa for reducing the error signal AR. In this regard, the error signal AR, may be directly passed at 102 to the switch controls 14a and 14b; however block 103 in FIG. 2 broadly signifies the apparatus and step of generating a usable and maintainable correction signal AF in response to AR input. The correction signal AF may thus be passed tothe switch controls 14a and 14b along with the error signal AR, so that when the standard frequency f1 to the comparator 101 is removed, the maintained correction signal AF will continue to be transmitted to the controls 14a and 14b for much more accurate drift compensation as respects f1.

Referring back to FIG. 1, the comparator indicated generally at 101 is in the form of a phase detector to repeatedly and quantitatively sample the phase difference lug-pol or error between f1 and fo. The particular sampling apparatus illustrated includes ip-flops 104 and 105 which are adapted to be set by positive going axis crossings of the signals of frequencies f1 and f., respectively. In addition, a reset driver 106 has its output connected with lthe reset inputs of the flip-flops, and its input connected with the flip-flop output leads 107 and 108 through an AND gate 109. The flip-flop outputs control current switches 110 and 111 connected with positive and negative current sources 112 and 113. The operation is such that the amount of positive or negative current transmitted at 114 in charging or discharging relation to the capacitor 115 is controlled by the phase difference rbi-qo or rho-pi between fo and fi, as is also indicated in FIG. 3.

The voltage VD at the capacitor is applied to the comparator 101a, which establishes up and down threshold voltage levels 'at 120 and 121. Each time the capacitor voltage increases or decreases to the up or down threshold levels, the comparator produces an error pulse, and the pulse train so produced corresponds to the error signal AR and has a frequency substantially proportional lto the phase difference iqs-qhol. If that phase difference is relatively small, it will take longer to charge or discharge the capacitor 115 to threshold level, so that the frequency of the error signal AR will be relatively lower, and vice versa. Switch 122 is suitably operated as indicated at 122a to discharge the capacitor each time the capacitor voltage arrives at an up or down (positive or negative) threshold level.

The error signal AR is directly applied via feedback paths 123, 124, 125, 126 and 20 to the switch control 14, through suitable dividers 127 and 128 and through a suitable slew (acquisition) and track (operate) switch 129. The latter in slew-mode by-passes AR around divider 127. In this regard, the feedback connection to the control 14 is such 4as to alter fo for reducing the error signal AR, as for example reducing its frequency; however, assuming the removal of the frequency standard AR will not exist, and f1 will resume its slow drift rate in the absence of what will next be described in the feedback channels.

As previously mentioned in the introduction, the invention further contemplates generating a maintainable correction signal AF corresponding to a time derivative of the error signal AR, and using the correction signal in the compensating operation upon f1. For example, the feedback channel means includes means to generate and transmit the correction signal AF1, corresponding to the first derivative with respect to time of the error signal, and expressed as follows:

As one example, a variable pulse rate generator 130 is connected in feedback leg 131 -along with a suitable divider 132, the generator generating the maintainable first derivative for application to the control 14. The maintainable correction signal may also include another term AF2 corresponding to the second derivative with respect to time of the error signal, as expressed as follows:

As one example, another variable pulse rate generator 133 is connected in feedback leg 134, along with a suitable divider 135, the generator generating the maint-ainable second derivative for application to the control 14. Since leg 134 is in series with leg 131, variable pulse rate generator 133 operates upon the first derivative output of variable pulse rate generator 130. A suitable switch 136 is operable in track mode to connect divider in series with generator 133, or in slew (acquisition) mode to by-pass the divider via path 137.

Leg 126 by-passes AR and AF, around the leg 134, so that at the sum location 139, the error and correction signals AR, AFI and AF2 are added for application at 20 to the control 14. When AR is removed as a result of removal of the comparison standard 140 source of f1, the correction signals AFl and AF2 will be maintained and applied to the control 14 to keep f1 from drifting, or otherwise greatly inhibit its drifting relative to f1. In other words, the influence of f, will long remain, even though it is removed. This result has great importance, as for example in regard to maintaining oscillators on board satellites in driftless condition, after their disconnection from frequency standards on earth prior to launch.

I claim:

1. In apparatus of the character described, a generator to produce a signal frequency f1 subject to drift, phase splitting means responsive to the received signal frequency f1 to produce multiple outputs of frequency f1 respectively phase displaced so as to cancel if added, means connected to be responsive to an error signal for selectively passing `and variably amplitude modulating different of said multiple output signals and thereafter combining the amplitude modulated signals to produce a version fo of f1, and means to compare fo with the output of a frequency standard to derive said error signal.

2. Apparatus of the character described, comprising a generator to produce a signal frequency f1 subject to drift, means operating upon said produced signal frequency f1 to derive a version fo of f1, means to compare fo with the output f1 of a frequency standard to derive a first error signal related to said drift, and feedback channel means to transmit a version of said error signal to said operating means in compensating relation to alter f., for reducing said error signal and to generate and transmit to said operating means maintainable correction signal corresponding to a time derivative of said error signal, said operating means including phase shifting -means responsive to the received signal frequency f1 to produce multiple outputs of frequency f1 and respectively phase displaced so as to cancel if added, and means connected to be responsive to said error signal for selectively passing and variably amplitude modulating different of said multiple output signals and thereafter combining the amplitude modulated signals to produce said version fo.

3. Apparatus as defined in claim 2 in which said feedback channel means includes means to generate and transmit said correction signal corresponding to substantially the first derivative with respect to time of said error signal.

4. Apparatus as defined in claim 3 in which said feedback channel means includes means to generate and transmit said correction signal corresponding to substantially the first and second derivatives with respect to time of said error signal.

5. Apparatus as defined in claim 3 in which said correction signal generating means comprises a variable pulse rate generator.

6. Apparatus as defined in claim 4 in which said rst and second derivative correction signal generating means comprise variable pulse rate generators.

3,850,658 7 8 7. Apparatus as defined in claim 2 in which said means References Cited for selectively passing -and variably amplitude modulating UNITED STATES PATENTS different of said multiple output signals includes a netating means includes switch control means responsive to l.

said version of the error signal to operate said network ROY LAKE Plmary Examiner' switches in controlled sequence. JOHN KOMINSKI, Examiner. 

1. IN APPARATUS OF THE CHARACTER DESCRIBED, A GENERATOR TO PRODUCE A SIGNAL FREQUENCY F1 SUBJECT TO DRIFT, PHASE SPLITTING MEANS RESPONSIVE TO THE RECEIVED SIGNAL FREQUENCY F1 TO PRODUCE MULTIPLE OUTPUTS OF FREQUENCY F1 RESPECTIVELY PHASE DISPLACED SO AS TO CANCEL IF ADDED, MEANS CONNECTED TO BE RESPONSIVE TO AN ERROR SIGNAL FOR SELECTIVELY PASSING AND VARIABLY AMPLITUDE MODULATING DIFFERENT OF SAID MULTIPLE OUTPUT SIGNALS AND THEREAFTER COMBINING THE AMPLITUDE MODULATED SIGNALS TO PRODUCE A VERSION F0 OF F1, AND MEANS TO COMPARE F0 WITH THE OUTPUT OF A FREQUENCY STANDARD TO DERIVE SAID ERROR SIGNAL. 